I have a serial output of a verilog module I'd like to testbench using system-verilog.
Posts about Verilog code for RAM and Testbench written by kishorechurchil. 2 to 4 decoder HDL Verilog Code. This page of verilog sourcecode covers HDL code for 2 to 4 decoder using verilog programming language. The fig-1 depicts 2 to 4 decoder schematic symbol and following is the truth table for the same.
The output, called 'SO' will output something like 8'hC6 given the correct serial input 'SI' with a value of say 8'h9A.
Is there an easy way to encode / decode serial IOs without having to explicitly describe each signal?
For example:
It looks like a jumbled mess and is barely readable. I'd very much like to just write
but obviously this doesn't work. Any advice or examples would be more than welcome. Thanks in advance.
N8TRON8TRO
2 Answers
Try a sequence and refer to IEEE Std 1800-2012 section 16.10 (Local variables):
This is equivalent to the the assertion provided and is more readable.
Do note the
local
keyword which will treat expected
as a variable rather then a reference and allows you to pass constant (e.g. 8'h9A
, 8'hC6
) and still allows you pas net references. See IEEE Std 1800-2012 section 16.8.2 (Local variable formal arguments in sequence declarations) for more.Here is a simple test bench to prove the assertion. I'm driving
SO
because I don't have a real DUT and I want to demonstrate both a pass & fail scenario.GregGreg
You usually don't use assertions to describe checks on data items, but on control signals. What you need in this case is to collect your whole input stream into a 16bit vector, collect you whole output stream and check that what you got on the SO line matches what you're supposed to get (some transformation of what was on the SI line). Etihad group of companies scam.
My SystemVerilog is rusty, but I'll give you a quick example of what I mean. Be aware that it's not compilable.
Hope it gives you an idea.
Tudor TimiTudor Timi
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I have to create the verilog code and testbench for this schematic.
I have the design for it here.
Here is what I have for the testbench so far.
Now I guess the part I am having issue with is how can I convert that number into those 4 inputs that are being used in the schematic. Or is there a better way to go about doing this?
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user2680027
1 Answer
Here is a simple way using the concatenation operator:
Yes, there are better ways to verify logic. The first thing to do is to introduce random values (refer to the
$urandom
functions in the IEEE Std 1800-2009). Of course, you also need to perform checks of your output using a model, which in your case is trivial.Depending on how much time (and training) you have, you could adopt a standard flow, such as the Universal Verification Methodology (UVM). People build careers around verification.
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